Many integrated circuits, such as memory devices and microprocessors, for example, require a continuous clock signal having a relatively constant duty cycle of ideally 50 percent. A 50 percent duty cycle is generally considered ideal for clocking signals which allows for maximum timing flexibility within integrated circuits, such as complementary metal oxide semiconductor (CMOS) logic. It is well appreciated in the art that the symmetry of a clock signal produced by a semiconductor circuit, such as a logic circuit, shifts away from an ideal 50 percent duty cycle as a result from module, card, and board wiring mismatch, and from semiconductor process variations. The resulting asymmetry in the clock signal, which represents an appreciable deviation from an ideal 50 percent duty cycle, can result in a number of operational anomalies, including reducing the maximum frequency of operation.
A number of circuit implementations have been developed in an attempt to address duty cycle asymmetry problems associated with clock signals and other types of time-varying signals. Several disadvantages of known clock signal circuit arrangements include their complexity, the large circuit space required for implementation, and increased difficulty and expense of manufacture.
There exists a keenly felt need for an apparatus and method for correcting asymmetry in the duty cycle of an AC or time-varying signal, such as a differential clock signal. There exists a particular need for such an apparatus and method which may be implemented with minimal complexity and one that may be implemented using present and future semiconductor fabrication technologies. The present invention fulfills these and other needs.